An increase in the operation frequency and power density of a semiconductor device requires a decrease in the unit cell dimension of the device. An approach used to reduce gate length and the unit cell size is to orient the current flow in the vertical direction. The vertical field effect transistor (VFET) has several advantages over a standard lateral FET for high frequency, high power applications. The VFET eliminates parasitic capacitance and conductance from the substrate and also provides higher breakdown voltage by passing the current flow in the bulk of the material instead of the device surface. Further, since the ohmic contacts and device channel are aligned vertically, the current density per unit of surface area is much higher than in a lateral FET. This means that for the same surface area VFETs will have much higher power than lateral FETs.
Silicon vertical MOSFETs have been used widely as power devices, and methods of manufacturing have been reported. However, intrinsic material properties of GaAs such as larger bandgap and higher mobility, offers 1.6 times greater breakdown field and 5 to 8 times lower on-resistance compared to Si, which guarantees the superior performance for high frequency, high power operation.
An early GaAs VFET device was a static induction transistor in which adjacent gates were made in V grooves by a diffusion process. The gate-gate spacing was made wide enough such that the channel was never pinched-off and the device was operated in the linear range. See Jun-Ichi Nishizawa, Takeshi Terasaki, and Jiro Shibata, "Field-Effect Transistor Versus Analog Transistor (Sctatic Induction Transistor)", IEEE Transactions on Electron Devices, Vol. ED-22, No. 4, April 1975, pp. 185-197.
To effectively pinch-off the channel, an electron beam lithography technique was used to pattern the ohmic contact on the top and a dual angle evaporation was subsequently used to deposit the gate metal. See: U. Mishra, P. A. Maki, J. R. Wendt, W. Schaff, E. Kohn, L. F. Eastman, "Vertical Electron Transistor (VET) in GaAs with a Heterojunction (AlGaAs--GaAs) Cathode", Electronics Letters, Vol. 20, No. 3, February 1984, pp. 145-146; and W. R. Frensley, B. Bayraktaroglu, S. Campbell, H. D. Shih, and R. E. Lehmann, "Design and Fabrication of a GaAs Vertical MESFET", IEEE Transactions on Electron Devices, Vol. ED-32, No. 5, May 1985, pp. 952-956. The drawback of this structure is the high manufacturing costs of electron beam lithography, reproducibility problems with the angle evaporation, and the large parasitic gate-drain capacitance. To reduce this capacitance and integrate VFETs into monolithic circuits, an air gap between the gate metal and the semiconductor surface was introduced.
Another method of making VFET devices is to overgrow epitaxial layers on the patterned substrate to form the desired channel spacing and gate doping type. See: U.S. Pat. No. 5,468,661, entitled "Method of making Power VFET Device", issued Jun. 17, 1993 and D. L. Plumton, H. T. Yuan, T. S. Kim, A. H. Taddiken, V. Ley, R. L. Kollman, I. Lagnado, and L. Johnson, "A Low on-Resistance, High-Current GaAs Power VFET", IEEE Electron Device Letters, Vol. 16, No. 4, April 1995, pp. 142-144. However, epitaxial regrowth is a complicated, expensive process.
Therefore, it would be highly advantageous to have an improved method of manufacturing GaAs VFETs.
It is a purpose of the present invention to provide a new and improved method of fabricating vertical field effect transistors.
It is another purpose of the present invention to provide a new and improved method of fabricating vertical field effect transistors with lower capacitance and lower ON-resistance.
It is a further purpose of the present invention to provide a new and improved method of fabricating vertical field effect transistors which is less expensive, less time consuming, and simpler than prior methods.